The 74LS112 dual J-K flip-flop has individual J, K, clock, and asynchronous sets and clear inputs for each flip-flop. When the clock goes HIGH, the inputs are enabled and data is accepted. When the clock pulse is HIGH, the logic level of the J and K inputs can be allowed to change, and the bi-stable will perform according to the truth table as long as the minimum set-up and hold time are observed. On the clock pulse's negative edge, input data is transferred to the outputs.